As the dimensions of transistors decrease, the thickness of the gate oxide must be reduced to maintain performance with the decreased gate length. However, in order to reduce gate leakage, high dielectric constant (high-k) gate oxide layers are used which allow greater physical thicknesses while maintaining the same effective thickness as would be provided by a typical gate oxide used in future technology nodes.
Additionally, as technology nodes shrink, in some integrated circuit (IC) designs, there has been a desire to replace the typically polysilicon gate electrode with a metal gate electrode to improve device performance with the decreased feature sizes. One process of forming the metal gate electrode is termed a “gate last” process in which the final metal gate electrode is fabricated “last” which allows for reduced number of subsequent processes, including high temperature processing, that must be performed after formation of the gate.
However, there are challenges to implementing such features and processes in complementary metal-oxide-semiconductor (CMOS) fabrication. As the gate length and spacing between devices decrease, these problems are exacerbated. For example, in a “gate last” fabrication process, it is difficult to achieve a perfect isolation between neighboring transistors because unwanted recesses are generated in an interlayer dielectric (ILD) layer after wet/dry etching a dummy gate. The recesses present in the ILD layer can become a receptacle of metals during subsequent processing thereby increasing the likelihood of electrical shorting and/or device failure.